This disclosure relates to data processing and storage, and more specifically, to management of a non-volatile memory system, such as a flash memory system, to support efficient management of page retirement utilizing page retirement classes.
NAND flash memory is an electrically programmable and erasable non-volatile memory technology that stores one or more bits of data per memory cell as a charge on the floating gate of a transistor or a similar charge trap structure. In a typical implementation, a NAND flash memory array is organized in blocks (also referred to as “erase blocks”) of physical memory, each of which includes multiple physical pages each in turn containing a multiplicity of memory cells. By virtue of the arrangement of the word and bit lines utilized to access memory cells, flash memory arrays can generally be programmed on a page basis, but are erased on a block basis.
As is known in the art, blocks of NAND flash memory must be erased prior to being programmed with new data. A block of NAND flash memory cells is erased by applying a high positive erase voltage pulse to the p-well bulk area of the selected block and by biasing to ground all of the word lines of the memory cells to be erased. Application of the erase pulse promotes tunneling of electrons off of the floating gates of the memory cells biased to ground to give them a net positive charge and thus transition the voltage thresholds of the memory cells toward the erased state. Each erase pulse is generally followed by an erase verify operation that reads the erase block to determine whether the erase operation was successful, for example, by verifying that less than a threshold number of memory cells in the erase block have been unsuccessfully erased. In general, erase pulses continue to be applied to the erase block until the erase verify operation succeeds or until a predetermined number of erase pulses have been used (i.e., the erase pulse budget is exhausted).
A NAND flash memory cell can be programmed by applying a positive high program voltage to the word line of the memory cell to be programmed and by applying an intermediate pass voltage to the memory cells in the same string in which programming is to be inhibited. Application of the program voltage causes tunneling of electrons onto the floating gate to change its state from an initial erased state to a programmed state having a net negative charge. Following programming, the programmed page is typically read in a read verify operation to ensure that the program operation was successful, for example, by verifying that less than a threshold number of memory cells in the programmed page contain bit errors. In general, program and read verify operations are applied to the page until the read verify operation succeeds or until a predetermined number of programming pulses have been used (i.e., the program pulse budget is exhausted).
Some NAND flash memories, referred to in the art as Single Level Cell (SLC), support only two charge states, meaning that only one bit of information can be stored per memory cell. Other NAND flash memories, referred to as Multi-Level Cell (MLC), Three Level Cell (TLC) and Quad Level Cell (QLC), respectively enable storage of 2, 3 or 4 bits information per cell through implementation of additional charge states. The higher storage density provided by NAND flash memories capable of storing multiple bits of information per cell often comes at the cost of higher bit error rates, slower programming times, and lower endurance (e.g., in terms of lifetime program/erase (P/E) cycle counts).
In general, it is common for subsets of a NAND flash memory exhibiting relatively high bit error rates to be retired, for example, as an error threshold is reached. While many NAND flash memories retire subsets of memory on a block-by-block basis, some NAND flash memories promote greater endurance by supporting retirement of individual physical pages of memory. However, employing sub-block granularity for retirement (and other flash management functions such as wear leveling) can lead to an undesirable increase in the amount of metadata that must be maintained as well an increase in implementation complexity.
The present application discloses a technique that provides improved endurance in a data storage system by enabling sub-block (e.g., page) retirement, while reducing the metadata required to track retired pages.